Operating Systems: Process Synchronization, Deadlocks & Memory Management
Operating system fundamentals form up to 25% of technical interview questions for government IT and scientist posts. In this module, we break down critical concepts, race conditions, semaphores vs mutex, Banker algorithm, and page replacement techniques.
In-Depth Interview Questions & Model Solutions
Q1What is the precise difference between a Mutex and a Counting Semaphore in kernel-level programming?
A Mutex (Mutual Exclusion Object) is a locking mechanism with ownership semantics: only the thread that locked the mutex can unlock it. It has two states: locked (0) and unlocked (1). In contrast, a Counting Semaphore is a signaling mechanism with an integer counter initialized to N. Any thread can signal (V / post) or wait (P / wait) on the semaphore, allowing up to N concurrent threads into a critical section.
- Mutex has ownership: thread that acquires must release.
- Semaphore is a signaling primitive: thread A can wait and thread B can signal.
- Mutex handles Priority Inversion via Priority Inheritance protocol.
Q2Explain the 4 Coffman conditions for Deadlock and how modern kernels handle prevention vs detection.
The four necessary and sufficient Coffman conditions are: (1) Mutual Exclusion (at least one resource non-shareable), (2) Hold and Wait (process holds resources while requesting more), (3) No Preemption (resources cannot be forcibly confiscated), and (4) Circular Wait (closed loop of processes waiting for each other). Kernels prevent deadlock by eliminating one condition (e.g. total ordering of resources to break circular wait). In high performance Linux/BSD systems, the Ostrich algorithm is practically adopted, while real-time OS (RTOS) use Banker Algorithm or Resource Reservation.
- Mutual Exclusion, Hold & Wait, No Preemption, Circular Wait.
- Eliminating Circular Wait via Resource Hierarchy is most practical.
- Bankers algorithm requires priori knowledge of maximum resource demands.
Q3How does the TLB (Translation Lookaside Buffer) accelerate Virtual Address Translation?
The MMU uses the TLB as a high-speed associative hardware cache for Virtual-to-Physical page table mappings. When CPU generates a virtual address (VPN + Offset), it checks TLB first. On TLB Hit: Physical Frame Number (PFN) is returned in 1 clock cycle. On TLB Miss: Hardware page table walker or OS trap queries multi-level page tables in RAM (costing 2-4 memory accesses), loads entry into TLB, and resumes execution.
- TLB hit ratio is typically > 98%.
- Multi-level paging saves RAM at cost of latency, mitigated by TLB.
- Context switches require TLB flush unless tagged with ASID (Address Space ID).
Technical Panel Interview Strategy Tips
- Always draw page table translation diagrams on the whiteboard when asked in ISRO/BARC interviews.
- Explain practical real-world scenarios (e.g. how Linux slab allocator prevents memory fragmentation).