Embedded Systems: ARM Cortex, Memory Maps, DMA & Interrupt Handling
Microcontroller architecture, direct memory access (DMA), and low-level peripheral drivers for defense and avionics systems.
In-Depth Interview Questions & Model Solutions
Q1Compare I2C and SPI communication protocols in terms of wires, speed, topology, and arbitration.
I2C is a 2-wire synchronous half-duplex bus (SDA, SCL) using open-drain lines with pull-up resistors. It supports multi-master with hardware address arbitration, typical speeds: 100 kHz to 3.4 MHz. SPI is a 4-wire synchronous full-duplex protocol (MOSI, MISO, SCK, CS/SS) with push-pull drivers. It uses separate chip select lines for each slave, does not have hardware addressing, and achieves much higher speeds (10 - 50+ MHz).
- I2C: 2 wires, open-drain, multi-master arbitration, addressing built-in, lower speed.
- SPI: 4+ wires, push-pull, single master with multiple CS pins, faster, no ACK mechanism.
- CAN Bus is used in automotive/avionics for differential noise immunity.
Q2What is Interrupt Latency and what techniques are used in RTOS to minimize it?
Interrupt Latency is the time delay between the hardware assertion of an interrupt and the execution of the first instruction in the corresponding Interrupt Service Routine (ISR). To minimize it: (1) Keep ISRs short and offload heavy computation to bottom-halves/worker tasks. (2) Use hardware vector tables and nested vectored interrupt controllers (like ARM NVIC with tail-chaining). (3) Avoid disabling interrupts inside critical code sections; use lock-free ring buffers instead.
- ARM NVIC tail-chaining reduces context save/restore overhead to 6 clock cycles.
- Never call blocking functions (e.g. `sleep()` or `malloc()`) inside an ISR.
Technical Panel Interview Strategy Tips
- Explain volatile keyword in C: tells compiler not to cache variable in CPU register since external hardware can modify it.